Development of a triple well CMOS MAPS device with in-pixel signal processing and sparsified readout capabilities

none 39 The SLIM5 collaboration has designed, fabricated and tested several prototypes of CMOS Monolithic Active Pixel Sensors (MAPS). The key feature of these devices, with respect to traditional MAPS is to include, at the pixel level, charge amplification and shaping and a first sparsification structure that interfaces with on-chip digital readout circuits. Via the 3-well option of the applied View the MathML source ST-Microelectronics CMOS technology each pixel includes a charge preamplifier, a shaper, a discriminator, an output latch, while retaining a fill factor of the sensitive area close to 90%. The last device of the family was submitted on Q4 2006 and the tests are ongoing. On this sensor, an on-chip, off-pixel digital readout block (streamout data sparsification) was added to implement, to control and to readout a test matrix built up of 4×4 pixels. It is aimed at proposing solutions that will overcome the readout speed limit of future large-matrix MAPS chips. http://dx.doi.org/10.1016/j.nima.2007.07.135 none G. Batignani; S. Bettarini; F. Bosi; G. Calderini; R. Cenci; M. Dell'Orso; F. Forti P. ; M.A. Giorgi; A. Lusiani; G. Marchiori; F. Morsani; N. Neri; E. Paoloni; G. Rizzo1; J. Walsh; L. Gaioni; M. Manghisoni; V. Re; G. Traversi; M. Bruschi; A. Gabrielli; B. Giacobbe; N. Semprini; R. Spighi; M. Villa; A. Zoccoli; G. Verzellesi; C. Andreoli5; E. Pozzati; L. Ratti; V. Speziali; D. Gamba; G. Giraudo; P. Mereu; L. Bosisio; G. Giacomini; L. Lanceri; I. Rachevskaia; L. Vitale G. Batignani; S. Bettarini; F. Bosi; G. Calderini; R. Cenci; M. Dell'Orso; F. Forti P. ; M.A. Giorgi; A. Lusiani; G. Marchiori; F. Morsani; N. Neri; E. Paoloni; G. Rizzo1; J. Walsh; L. Gaioni; M. Manghisoni; V. Re; G. Traversi; M. Bruschi; A. Gabrielli; B. Giacobbe; N. Semprini; R. Spighi; M. Villa; A. Zoccoli; G. Verzellesi; C. Andreoli5; E. Pozzati; L. Ratti; V. Speziali; D. Gamba; G. Giraudo; P. Mereu; L. Bosisio; G. Giacomini; L. Lanceri; I. Rachevskaia; L. Vital

PixFEL: development of an X-ray diffraction imager for future FEL applications

A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with square pixels and a pixel pitch of 110 µm. Each cell includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, covering an input dynamic range from 1 to 104 photons and featuring single photon resolution at small signals at energies from 1 to 10 keV. The CSA output is processed by a time-variant shaper performing gated integration and correlated double sampling. Each pixel includes also a small area, low power 10-bit time-interleaved Successive Approximation Register (SAR) ADC for in-pixel digitization of the amplitude measurement. The channel can be operated at rates up to 4.5 MHz, to be compliant with the rates foreseen for future X-ray FEL machines. The ASIC has been designed in order to be bump bonded to a slim/active edge pixel sensor, in order to build the first demonstrator for the PixFEL (advanced X-ray PIXel cameras at FELs) imager

CMOS monolithic sensors in a homogeneous 3D process for low energy particle imaging

A 3D, through silicon via microelectronic process, capable of face-to-face assembling two 130 nm CMOS tiers in a single bi-layer wafer, has been exploited for the design of monolithic active pixels (MAPS), featuring a deep N-well (DNW) collecting electrode. They are expected to improve on planar CMOS DNW MAPS in terms of charge collection efficiency since most of the PMOS transistors in the front-end electronics, with their N-wells, can be moved to a different layer from that of the DNW sensor. The vertical integration process also requires that one of the two CMOS tiers be thinned down to a mere 6 m to expose the through silicon vias and contact the sandwiched circuits. In this work, results from device simulations of 3D MAPS will be presented. The aim is to evaluate the potential of such a thin sensitive substrate in the detection of low energy particles (in the tens of keV range), in view of possible applications to biomedical imaging

Results from CHIPIX-FE0, a Small Scale Prototype of a New Generation Pixel Readout ASIC in 65nm CMOS for HL-LHC

CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 μm2. It is fully functional, can work at low thresholds down to 250e− and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex digital chip. CHIPIX65-FE0 has been irradiated up to 600 Mrad and is only marginally affected on analog performance. Further irradiation to 1 Grad will be performed. Bump bonding to silicon sensors is now on going and detailed measurements will be presented. The HL-LHC accelerator will constitute a new frontier for particle physics after year 2024. One major experimental challenge resides in the inner tracking detectors, measuring particle position: here the dimension of the sensitive area (pixel) has to be scaled down with respect to LHC detectors. This paper describes the results obtained by CHIPIX65-FE0, a readout ASIC in CMOS 65nm designed by the CHIPIX65 project as small-scale demonstrator for a pixel detector at the HL-LHC. It consists of a matrix of 64x64 pixels of dimension 50x50 um2 pixels and contains several pieces that are included in RD53A, a large scale ASIC designed by the RD53 Collaboration: two out of three front-ends (a synchronous and an asynchronous architecture); several building blocks; a (4x4) pixel region digital architecture with central local buffer storage, complying with a 3 GHz/cm2 hit rate and a 1 MHz trigger rate maintaining a very high efficiency (above 99%). The chip is 100% functional, either running in triggered or trigger-less mode. All building-blocks (DAC, ADC, Band Gap, SER, sLVS-TX/RX) and very front ends are working as expected. Analog performance shows a remarkably low ENC of 90e-, a fast-rise time below 25ns and low-power consumption (about 4μA/pixel) in both synchronous and asynchronous front-ends; a very linear behavior of CSA and discriminator. No significant cross talk from digital electronics has been measured, achieving a low threshold of 250e-. Signal digitization is obtained with a 5b-Time over Threshold technique and is shown to be fairly linear, working well either at 80 MHz or with higher frequencies of 300 MHz obtained with a tunable local oscillator. Irradiation results up to 600 Mrad at low temperature (-20°C) show that the chip is still fully functional and analog performance is only marginally degraded. Further irradiation will be performed up to 1 Grad either at low or room temperature, to further understand the level of radiation hardness of CHIPIX65-FE0. We are now in the process of bump bonding CHIPIX65-FE0 to 3D and possibly planar silicon sensors during spring. Detailed results will be presented in the conference paper

First Measurements of a Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for Extreme Rate HEP Detectors at HL-LHC

A first prototype of a readout ASIC in CMOS 65nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50x50 um2 and the matrix consists of 64x64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35x35 um2. ENC value is below 100e- for an input capacitance of 50 fF and in-time threshold below 1000e-. Leakage current compensation up to 50 nA with power consumption below 5 uW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm2, trigger rates up to 1 MHz and trigger latency of 12.5 us. The total power consumption per pixel is below 5uW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper

Predicting needlestick and sharps injuries in nursing students: Development of the SNNIP scale

© 2020 The Authors. Nursing Open published by John Wiley & Sons Ltd. Aim: To develop an instrument to investigate knowledge and predictive factors of needlestick and sharps injuries (NSIs) in nursing students during clinical placements. Design: Instrument development and cross-sectional study for psychometric testing. Methods: A self-administered instrument including demographic data, injury epidemiology and predictive factors of NSIs was developed between October 2018–January 2019. Content validity was assessed by a panel of experts. The instrument's factor structure and discriminant validity were explored using principal components analysis. The STROBE guidelines were followed. Results: Evidence of content validity was found (S-CVI 0.75; I-CVI 0.50–1.00). A three-factor structure was shown by exploratory factor analysis. Of the 238 participants, 39% had been injured at least once, of which 67.3% in the second year. Higher perceptions of “personal exposure” (4.06, SD 3.78) were reported by third-year students. Higher scores for “perceived benefits” of preventive behaviours (13.6, SD 1.46) were reported by second-year students

Recent results and plans of the 3D IC consortium

Vertical integration technologies are very promising in view of the demanding requirements set by the future High Energy Physics (HEP) experiments at particle accelerators. In these applications silicon pixel sensors will be required to integrate advanced functionalities and to have low mass and small pitch. This paper presents the activities of the 3D IC consortium and describes the designs submitted in the first multi-project (MPW) run taking advantage of a homogeneous vertical integration technology

A Charge Sensitive Amplifier in a 28 nm CMOS Technology for Pixel Detectors at Future Particle Colliders

This paper is concerned with the design of a Charge Sensitive Amplifier (CSA) in a 28 nm CMOS technology. The CSA discussed in this work is conceived for High Energy Physics (HEP) experiments at next-generation colliders, where pixel detectors will be read out by specific front-end chips, typically including a CSA exploited for charge-to-voltage conversion of the signal delivered by the sensor. The main analog performance parameters of the CSA, also referred to as the pre-amplifier, are assessed here by means of specific Spectre simulations, which are meant to evaluate the behavior of the analog processor in terms of noise, linearity and capability to compensate for very large detector leakage currents. Noise simulations revealed an equivalent noise charge close to 75 electrons rms for typical operating conditions. Up to 50 nA sensor leakage current can be compensated for thanks to the CSA Keummenacher feedback network. The total current consumption of the CSA is close to 2.2 µA, which, together with a power supply of 0.9 V, translates to a power consumption of 2.0 µW